Feature Overview of the new DMA Flex IP Core
Outstanding feature of the new version is the simultaneous transmisson of up to 16 Streaming Channels in separate memory buffers of the host system. The user can use his own clockdomain and can adjust the datawidth for each channel. The events „Start of Frame“, „End of Frame“ and „End of line“ are supported and control the storage in memory and can be used as interrupt triggers.
Parametrizable Data FIFOs in the datachannels of the IP were integrated in order to realize a priority scheme. This prevents high priority channels from being blocked by low priority channels.
The IP Core targets not only the field of streaming applications but also Coprocessor Applications. Due to the integrated DMA Read Module the IP Core reads data from a datasource, processes the data and writes it to the target.
The IP Core is also featuring the continuous monitoring of Signal Integrity, where CRC Errors on the PCIe Link are permanently counted. With this feature it is possible to detect soldering problems during productional tests. Especially security critical applications greatly benefit from this feature.