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Video DMA IP Core
FPGA Design with PCI-Express Interface for Xilinx and Intel FPGAs

Ethernet over PCI Express

The high-channel-count IP core (HCC) allows you to connect Ethernet links to your FPGA via PCI Express. The HCC core provides the RX and TX AXI stream interfaces that have to be connected to an Ethernet MAC of your choice. If you are targeting, state of the art 10/100/1000 ethernet links, or high-performance 10G/40G ethernet, the performance is only limited by the PCI Express bandwidth. Our IP package includes the IP Core with a full functioning reference design and also a powerful device driver, that integrates the ethernet link natively into the operating system. The new link can be accessed by the user in the same way as existing ethernet links.

Since our HCC IP core supports the PCIe multi-function feature, it is possible to implement more than one ethernet link and to add user specific DMA . Each function has its own dedicated device driver which clearly separates each unit on the software level.

How many functions there are supported, is defined by the number of “physical PCIe functions” by the FPGA vendor and varies between 4 and 8.

You will find more details in our application note

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